Basically, the central processing unit (CPU) of a computer system is not directly powered by a power supply. Because the intensity of the core voltage (Vcore) required by the CPU is varied with the actual load of the CPU, the intensity of the core voltage (Vcore) may change vary sharply according to the extremely heavy load or the extremely light load on the CPU. Voltage regulator module (VRM) is very widely equipped with the computer system for providing the core voltage (Vcore) to the CPU due to the VRM is designed to quickly provide the core voltage (Vcore) according to the requirement of the CPU.
FIG. 1 is a functional block diagram depicting a conventional single-phase VRM. The single-phase VRM comprises a pulse-width-modulation (PWM) controller 10, a PWM driver 12, and a PWM circuit 14, where a PWM signal is transmitted to the PWM driver 12 from the PWM controller 10.
Furthermore, the PWM driver 12 comprises a steering logic circuit 16 and two driving circuits 18 and 20. A first signal and a second signal are transmitted to the two driving circuits (18, 20) respectively from the steering logic circuit 16 according to the PWM signal. A first driving signal (S1) is outputted from the driving circuit 18 according to the first signal. A second driving signal (S2) is outputted from the driving circuit 20 according to the second signal.
Furthermore, the PWM circuit 14 comprises a upper power field effect transistor (FET) (M1), a lower power FET (M2), an output choke (L), a current sense resistor (Rs), and a output capacitor (Co), where the upper power FET (M1) and the lower power FET (M2) is a n-type FET. The upper power FET (M1) comprises a drain (D) connected to a voltage source (Vcc, +12V); a gate (G) to which the first driving signal (S1) is inputted; a source (S) is connected to a first end of the output choke (L). The lower power FET (M2) comprises a drain (D) connected to the first end of the output choke (L); a gate (G) to which the second driving signal (S2) is inputted; a source (S) is connected to ground (GND). The current sense resistor (Rs) is coupled between a second end of the output choke (L) and a Vcore-output end from which the core voltage (Vcore) is outputted. The output capacitor (Co) is coupled between the Vcore-output end and ground (GND). The current sense resistor (Rs), the output choke (L), and the output capacitor (Co) are combined as a RLC circuit.
Furthermore, the Vcore-output end is connected to a power layer of a motherboard (not shown), and the power layer is further connected to the CPU for providing the Vcore voltage to the CPU.
Via the first driving signal (SI) and the second driving signal (S2) respectively applied to the upper power FET (M1) and the lower power FET (M2), an output current (Io), originally from the voltage source (Vcc, +12V), is resulted in and outputted to the CPU from the Vcore-output end sequentially via the output choke (L) and the current sense resistor (Rs). Because the intensity of the output current (Io) is proportional to the load of the CPU, the operation mode of the CPU can be determined according to the intensity of the output current (Io), and the conventional single-phase VRM can dynamically modulate the output current (Io) to the CPU according to the operation mode of the CPU. If the CPU is operated in a heavy-load mode, the sense voltage (Vs) on the current sense resistor (Rs) is accordingly relative high. The relative high sense voltage (Vs) is then detected by a feedback logic circuit 21 arranged in the PWM controller 10. Then, a PWM signal with wider pulse widths, for informing the PWM driver 12 and the PWM circuit 14 to output a relative large output current (Io), is transmitted to the PWM driver 12 from the PWM controller 10. Alternatively, if the CPU is operated in a light-load mode, the sense voltage (Vs) on the current sense resistor (Rs) is accordingly relative low. The relative low sense voltage (Vs) is then detected by the feedback logic circuit 21. Then, a PWM signal with narrower pulse widths, for informing the PWM driver 12 and the PWM circuit 14 to output a relative small output current (Io), is transmitted to the PWM driver 12 from the PWM controller 10.
A single-phase VRM means a VRM is constituted by only one PWM driver 12 and only one PWM circuit 14. Accordingly, a multi-phase VRM means a VRM is constituted by more than one PWM drivers and corresponding number of PWM circuits. Because the CPU today consumes more and more power, the multi-phase VRM capable of providing a stable core voltage (Vcore) is more commonly used on the motherboard.
FIG. 2 is a functional block diagram depicting a conventional eight-phase VRM. The eight-phase VRM comprises a PWM controller 22, eight PWM drivers (24, 26, 28, 30, 32, 34, 36, 38), and eight PWM circuits (40, 42, 44, 46, 48, 50, 52, 54). Furthermore, each PWM circuit (40, 42, 44, 46, 48, 50, 52, 54) comprises two power FETs (M1, M2) and a RLC circuit. Furthermore, the eight PWM signals (PWM1˜PWM8) are respectively transmitted to the eight PWM drivers (24, 26, 28, 30, 32, 34, 36, 38) from the PWM controller 22.
Furthermore, the eight PWM drivers (24, 26, 28, 30, 32, 34, 36, 38) and the eight PWM circuits (40, 42, 44, 46, 48, 50, 52, 54) respectively constitute eight phase circuits (210, 220, 230, 240, 250, 260, 270, 280), where each of the phase circuit (210, 220, 230, 240, 250, 260, 270, 280) comprises a Vcore-output end connected to a power layer of the motherboard (not shown) for providing the core voltage (Vcore) to the CPU. As described above, the output currents (Io) outputted to the CPU from the eight phase circuits (210, 220, 230, 240, 250, 260, 270, 280) are respectively controlled by the eight PWM signals (PWM1˜PWM8). Furthermore, the current, consumed by the CPU and is named CPU current (I_CPU), is the sum of the eight output currents (Io) outputted from the eight phase circuits (210, 220, 230, 240, 250, 260, 270, 280). Furthermore, the function of the eight PWM drivers (24, 26, 28, 30, 32, 34, 36, 38) is exactly same as the PWM driver 12 (FIG. 1). The function of the eight PWM circuits (40, 42, 44, 46, 48, 50, 52, 54) is exactly same as the PWM circuit 14 (FIG. 1).
With the increasing number of phases in the multi-phase VRM, the reliability and the stability of the operating frequency and the core voltage of the CPU are accordingly secured. However, more phases in a multi-phase VRM also brings more unnecessary power waste due to the impedance factor resulted in the multi-phase VRM itself. Moreover, according to the related research, the efficiency is relative low if the multi-phase VRM is operated at a relative light load.
FIG. 3A is a scheme illustrating an efficiency curve of a conventional multi-phase VRM (only a VRM switched to operate between four phases and eight phases is took as an example). As depicted in FIG. 3A, an optimal efficiency is obtained if all the eight phases are active for providing the eight output currents (Io) to the CPU when the CPU is operated at a heavy load (I-CPU greater than I_CPUref) but only the four phases are active for providing four output currents (Io) to the CPU when the CPU is operated at a light load (I-CPU less than I_CPUref), where the I_CPUref stands for a predefined reference CPU current.
To aware of the present operation load of the CPU via comparing the CPU current (LCPU) with the reference CPU current (I_CPUref), a load detect circuit, usually implemented by a comparator, is introduced in the conventional multi-phase VRM. FIG. 3B is a scheme illustrating the load detect circuit (comparator) adopted in the conventional multi-phase VRM. First, the real CPU current (I_CPU) on the CPU and the predefined reference CPU current (I_CPUref) are proportionally converted to voltages, and the two voltages are then transmitted to two input ends (Iin+and Iin−) of the load detect circuit (comparator) 100. After the real CPU current (I_CPU) on the CPU is compared with the predefined reference CPU current (I_CPUref), a logic-low signal is outputted from an output end (O) of the load detect circuit (comparator) 100 if the real CPU current (I_CPU) consumed by the CPU is greater than the predefined reference CPU current (I_CPUref); or, a logic-high signal is outputted from the output end (O) of the load detect circuit (comparator) 100 if the real CPU current (I_CPU) consumed by the CPU is less than the predefined reference CPU current (I_CPUref). Afterwards, a specific number of active phases, for providing the output currents (Io) to the CPU, can be determined based on the logic signal outputted from the load detect circuit (comparator) 100. For example, if the CPU is detected to operate in a heavy-load mode by the load detect circuit 100, a logic-low signal is outputted from an output end (O) of the load detect circuit (comparator) 100, accordingly all the eight PWM signals (PWM1˜PWM8) are outputted to the eight phase circuits (210, 220, 230, 240, 250, 260, 270, 280) respectively from the PWM controller 22 (FIG. 2), so as all the eight phase circuits (210, 220, 230, 240, 250, 260, 270, 280) are active for providing eight output currents (Io) to the CPU. Alternatively, if the CPU is detected to operate in a light-load mode by the load detect circuit 100, a logic-high signal is outputted from the output end (O) of the load detect circuit (comparator) 100, accordingly only the first four PWM signals (PWM1˜PWM4) are outputted to the four phase circuits (210, 220, 230, 240) respectively from the PWM controller 22 (FIG. 2), so as only the first four phase circuits (210, 220, 230, 240) are active for providing four output currents (Io) to the CPU.
Because the first four phase circuits (210, 220, 230, 240) are always active no matter the CPU is determined to operate either in the heavy-load mode or the light-load mode, apparently the life hour of the devices in the first four phase circuits (210, 220, 230, 240) is shorter than that in the last four phase circuits (250, 260, 270, 280) after a long term.